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PE46120 product specification monolithic phase & amplit ude controller, 1.8C2.2 ghz ?2014-2015, peregrine semiconductor corporation. all rights reserved. ? headquarters: 9380 carroll park drive, san diego, ca, 9 2121 product specification doc-54655-6 C (5/2015) www.psemi.com features ? 90 phase splitter ? 5-bit digital phase shifter, 87.2 range, 2.8 resolution ? 4-bit digital step attenuator, 7.5 db range, 0.5 db resolution ? high power handling and linearity ? p0.1db of +35 dbm ? input ip3 of +60 dbm ? packaging ? 32-lead 6 6 mm qfn applications ? wireless infrastructure ? macro cells ? small cells (micro, pico) ? distributed antenna systems (das) ? precision phase shifter ? dual polarization antenna alignment ? analog linearization techniques product description the PE46120 is a harp? technology-enhanced monolith ic phase and amplitude controller (mpac) designed for precise phase and amplitude control of two independent rf paths. it optimizes system performance while reducing manufacturing costs of transmitters that use symmetric or asymmetric power amplifier designs to efficiently process signals with large peak-to-average ratios. this monolithic rfic integrates a 90 rf splitter, digita l phase shifters and a digital step attenuator along with a low voltage cmos serial interface. it can cover a phase range of 87.2 in 2.8 steps and an attenuation range of 7.5 db in 0.5 db steps, while providing excellent phase and amplitude accuracy from 1.8?2.2 ghz. the PE46120 also features exceptional linearity, high output port-to-port isolation and extremely low power consumption relative to competing module solutions . it is offered in a 32-lead 6 6 mm qfn package. the PE46120 is manufactured on peregrine?s ultracmos ? process, a patented variation of silicon-on-insulator (soi) technology on a sapphire substrate, offering the perf ormance of gaas with the economy and integration of conventional cmos. peregrine?s harp? technology enhancements deliver high linearity and excellent harmonics performance. figure 1 ? PE46120 block diagram rf in v dd gnd sdi clk le ds sdo rf out2 -90 0 rf out1 sp enb 7.5 db 0.5 db lsb 0 db 87.2 2.8 lsb 87.2 2.8 lsb digital interface 3 serial interface
PE46120 monolithic phase & amplitude controller page 2 doc-54655-6 C (5/2015) www.psemi.com absolute maximum ratings exceeding absolute maximum ratings listed in table 1 may cause permanent damage. operation should be restricted to the limits in table 2 . operation between operating range maximum and absolute maximum for extended periods may reduce reliability. esd precautions when handling this ultracmos device, observe the same precautions as with any other esd-sensitive devices. although this device contains circuitry to protect it fr om damage due to esd, precautions should be taken to avoid exceeding the rating specified in table 1 . latch-up immunity unlike conventional cmos devices, ultracmos devices are immune to latch-up. table 1 ? absolute maximum ratings for PE46120 parameter/condition min max unit supply voltage, v dd ?0.3 5.5 v digital input voltage ?0.3 3.6 v maximum input power 35 dbm storage temperature range ?65 +150 c esd voltage hbm (1) all pins rf pins to gnd 500 1000 v v esd voltage cdm, all pins (2) 1000 v notes: 1) human body model (mil-std 883 method 3015.7). 2) charged device model (jedec jesd22-c101).
PE46120 monolithic phase & amplitude controller doc-54655-6 C (5/2015) page 3 www.psemi.com recommended operating conditions table 2 lists the recommending operating condition for pe 46120. devices should not be operated outside the recommended operating conditions listed below. table 2 ? recommended operating condition for PE46120 parameter min typ max unit supply voltage, v dd (1) 2.3 5.5 v supply current 350 500 a digital input high 1.17 3.6 v digital input low 00 . 6 v digital input leakage 10 20 a rf input power, cw 29 dbm rf input power, pulsed (2) 32 dbm operating temperature range ?40 +25 +105 c notes: 1) product performance does not vary over v dd . 2) pulsed, 5% duty cycle of 4620 s period.
PE46120 monolithic phase & amplitude controller page 4 doc-54655-6 C (5/2015) www.psemi.com electrical specifications table 3 provides the PE46120 key electrical specifications at 25 c, v dd = 2.3?5.5v, 50 ? , unless otherwise specified. switching frequency the PE46120 has a maximum 25 khz switching frequency. the switching frequency is defined to be the rate at which the PE46120 can be continuously toggled across attenuation and phase states. table 3 ? PE46120 electrical specifications parameter path condition min typ max unit operating frequency 1.8 2.2 ghz insertion loss rf in to rf outx reference phase and minimum attenuation state. includes 3 db from power divider. 6.9 7.4 db input return loss rf in 1.8?2.2 ghz 15 db output return loss rf out1 or rf out2 1.8?2.2 ghz 15 db isolation rf out1 to rf out2 1.8?2.2 ghz reference phase and minimum attenuation state. 27.5 30 db input 0.1db compression point (1) rf in to rf out1 or rf out2 1.8?2.2 ghz 35 dbm input ip3 rf in to rf out1 or rf out2 1.8?2.2 ghz 60 dbm switching time (2) 50% le to 90% or 10% rf final value 980 1220 ns phase shift range rf in to rf out1 or rf out2 87.2 deg phase step 2.8 deg relative phase shift rf out1 to rf out2 phase (rf out1 )?phase (rf out2 ) [same state] ?90 deg attenuation range rf in to rf out2 7.5 db attenuation step 0.5 db notes: 1) the input 0.1db compression point is a linearity figure of merit. refer to table 2 for the operating rf input power (50 ? ). 2) worst case state transition. all bits changing.
PE46120 monolithic phase & amplitude controller doc-54655-6 C (5/2015) page 5 www.psemi.com control logic table 4 ? table 10 provide the control logic truth tables for the PE46120. table 4 ? bit descriptions c0 channel register select c0 = l, channel rf out1 register select c0 = h, channel rf out2 register select m0?m3 attenuation setting per channel p0?p4 phase shift setting per channel s0?s3 spare bits table 5 ? 14-bit word q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 c0 s3 s2 m3 m2 m1 m0 p4 p3 p2 p1 p0 s1 s0 1 ??????4522.511.25.62.8?? 2 ? ? 4 2 1 0.5 45 22.5 11.2 5.6 2.8 ? ? table 6 ? serial truth table C phase setting q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 phase shift setting c0 s3 s2 m3 m2 m1 m0 p4 p3 p2 p1 p0 s1 s0 1/2 ? ? 4 2 1 0.5 45 22.5 11.2 5.6 2.8 ? ? xxxxxxx lllllxx ref phase xxxxxxx llllhxx 2.8 deg xxxxxxxl l lhlxx 5.6 deg xxxxxxxl lhl lxx 11.25 deg xxxxxxxlhl l lxx 22.5 deg xxxxxxxh llllxx 45 deg xxxxxxx hhhhhxx 87.2 deg
PE46120 monolithic phase & amplitude controller page 6 doc-54655-6 C (5/2015) www.psemi.com table 7 ? serial truth table C attenuation setting (rf out2 ) q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 amplitude setting c0 s3 s2 m3 m2 m1 m0 p4 p3 p2 p1 p0 s1 s0 1 ? ? ? ? ? ? 45 22.5 11.2 5.6 2.8 ? ? 2 ? ? 4 2 1 0.5 45 22.5 11.2 5.6 2.8 ? ? hxxllll xxxxxxxref insertion loss hxxl l lhxxxxxxx 0.5 db hxxl lhlxxxxxxx 1 db hxxlhl lxxxxxxx 2 db hxxhl l lxxxxxxx 4 db hxxhhhh xxxxxxx 7.5 db table 8 ? default state settings at power up (rf out1 ) ds setting q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 default setting at power up c0 s3 s2 m3 m2 m1 m0 p4 p3 p2 p1 p0 s1 s0 1/2 ? ? 4 2 1 0.5 45 22.5 11.2 5.6 2.8 ? ? ds = 0??????? lllll?? 0 db 0 deg ds = 1??????? h llll?? 0 db 45 deg table 9 ? default state settings at power up (rf out2 ) ds setting q13 q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0 default setting at power up c0 s3 s2 m3 m2 m1 m0 p4 p3 p2 p1 p0 s1 s0 1/2 ? ? 4 2 1 0.5 45 22.5 11.2 5.6 2.8 ? ? ds = 0???lllllllll?? 0 db 0 deg ds = 1???hhhhh llll?? 7.5 db 45 deg
PE46120 monolithic phase & amplitude controller doc-54655-6 C (5/2015) page 7 www.psemi.com table 10 ? serial interface timing characteristics (1) parameter/condition min max unit serial clock frequency, f clk (2) 0.032 26 mhz serial clock period, t sclk 40 ns serial clock high time, t sclkh 20 ns serial clock low time, t sclkl 20 ns serial data output propagation delay from clk falling edge, t ov (10 pf) 9ns latch clock pulse width high, t lclkh 10 ns serial data input setup time from clk rising edge, t su 5n s serial data input hold time from clk rising edge, t h 2n s serial data output hold time from clk rising edge, t oh 1.6 ns serial clock rising edge setup time to latch clock rising edge, t settle 27 ns sdo drive strength (3) 15 pf notes: 1) v dd = 2.3v?5.5v, ?40 c < t a < +105 c, unless otherwise specified. 2) limited by test duration not static logic design. synchronous to clock. minimum clock frequency tested = 32 khz. 3) sdo maximum capacitive load drive strength for f clk = 26 mhz with a 1.8v swing.
PE46120 monolithic phase & amplitude controller page 8 doc-54655-6 C (5/2015) www.psemi.com programming options serial interface the serial interface is a 14-bit serial-in shift register with two parallel-out channel registers rf out1 and rf out2 buffered by a transparent latch. the 14 bits are comprised of four bits defining the attenuation setting and five bits for the phase shift setting. channel register rf out1 and rf out2 selection is determined by the value of the c0 bit contained as part of the 14-bit program word. the serial interface is controlled using three cmos compatible signals: serial data in (sdi), clock (clk) and latch enable (le). the sdi and clk inputs allow data to be serially entered into the shift register. serial data is clocked in starting with two spare bits first and then the phase setting lsb. the shift register must be loaded while le is held low to prevent the internal channel register values from changing as data is entered. the le input should then be toggled high, latching the new data into the PE46120. sdo is a clock delayed reply of the user?s input sdi command for functional confirmation. phase shift and attenuation setting truth tables are listed in table 6 and ? table 7 . the serial timing diagram is illustrated in figure 2 and associated ac characteristics are listed in table 10 . power-up control settings the PE46120 will power up in one of two default states depending upon the setting of the default state (ds) pin, as defined in table 8 and table 9 . no specific signal sequencing is required for the default state to be set and active once v dd is applied. figure 2 ? latched buffered sdo serial interface sclk sdi sdo channel 1 register data channel 2 register data le s0 s1 p0 p1 p2 p3 p4 m0 m1 m2 m3 s2 s3 c0 01 s0 s1 p0 p1 p2 p3 p4 m0 m1 m2 m3 s2 s3 c0 s0 t ov t sclk t su t h t sclkh t lclkh t settle t oh default/current value default/current value new value new value t sclkl s1 p0 p1 p2 p3 p4 m0 m1 m2 m3 s2 s3 c0 s0 s1 p0 p1 p2 p3 p4 m0 m1 m2 m3 s2 s3 c0
PE46120 monolithic phase & amplitude controller doc-54655-6 C (5/2015) page 9 www.psemi.com typical performance data figure 3 ? figure 23 show the typical performance data at 25 c and v dd = 2.3?5.5v, 50 ? , unless otherwise specified figure 3 ? relative phase shift (rf out1 Crf out2 ) -100 -98 -96 -94 -92 -90 -88 -86 -84 -82 -80 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 phase delta (deg) frequency (mhz) phase(s21)-phase(s31)
PE46120 monolithic phase & amplitude controller page 10 doc-54655-6 C (5/2015) www.psemi.com figure 4 ? insertion loss (rf in to rf out1 ) -8 -7.8 -7.6 -7.4 -7.2 -7 -6.8 -6.6 -6.4 -6.2 -6 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 insertion loss (db) frequency (mhz) magnitude(s21) 1 1 800 2200 figure 5 ? insertion loss (rf in to rf out2 ) -8 -7.8 -7.6 -7.4 -7.2 -7 -6.8 -6.6 -6.4 -6.2 -6 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 insertion loss (db) frequency (mhz) magnitude(s31)
PE46120 monolithic phase & amplitude controller doc-54655-6 C (5/2015) page 11 www.psemi.com figure 6 ? insertion loss rf in to rf out2 (all rf out2 attenuation states) -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 insertion loss (db) frequency (mhz) 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5
PE46120 monolithic phase & amplitude controller page 12 doc-54655-6 C (5/2015) www.psemi.com figure 7 ? relative phase rf in to rf out1 (all rf out1 phase states) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 phase (deg) frequency (mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 figure 8 ? relative phase rf in to rf out2 (all rf out2 phase states) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 phase (deg) frequency (mhz) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
PE46120 monolithic phase & amplitude controller doc-54655-6 C (5/2015) page 13 www.psemi.com figure 9 ? input return loss (all states) -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 return loss (db) frequency (mhz)
PE46120 monolithic phase & amplitude controller page 14 doc-54655-6 C (5/2015) www.psemi.com figure 10 ? output return loss rf out1 (all rf out1 phase states) -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 return loss (db) frequency (mhz) figure 11 ? output return loss rf out2 (all rf out2 states) -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 return loss (db) frequency (mhz)
PE46120 monolithic phase & amplitude controller doc-54655-6 C (5/2015) page 15 www.psemi.com figure 12 ? isolation output ports (all states) -70 -60 -50 -40 -30 -20 -10 0 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 isolation (db) frequency (mhz)
PE46120 monolithic phase & amplitude controller page 16 doc-54655-6 C (5/2015) www.psemi.com figure 13 ? rf out1 insertion loss variation across all rf out2 states -8 -7.8 -7.6 -7.4 -7.2 -7 -6.8 -6.6 -6.4 -6.2 -6 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 insertion loss (db) frequency (mhz) figure 14 ? rf out1 phase variation across all rf out2 phase states -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 phase (deg) frequency (mhz)
PE46120 monolithic phase & amplitude controller doc-54655-6 C (5/2015) page 17 www.psemi.com figure 15 ? rf out1 insertion loss variation across rf out1 phase state -8 -7.8 -7.6 -7.4 -7.2 -7 -6.8 -6.6 -6.4 -6.2 -6 0 102030405060708090 insertion loss (db) phase state (deg) 1.8 ghz 2.0 ghz 2.2 ghz figure 16 ? rf out2 insertion loss variation across rf out2 phase state -8 -7.8 -7.6 -7.4 -7.2 -7 -6.8 -6.6 -6.4 -6.2 -6 0 102030405060708090 insertion loss (db) phase state (deg) 1.8 ghz 2.0 ghz 2.2 ghz
PE46120 monolithic phase & amplitude controller page 18 doc-54655-6 C (5/2015) www.psemi.com figure 17 ? rf out1 insertion loss variation across phase state (*) note: * across recommended rf out1 phase states for minimum insertion loss variation. -8 -7.8 -7.6 -7.4 -7.2 -7 -6.8 -6.6 -6.4 -6.2 -6 0 102030405060708090100 insertion loss (db) phase state (deg) 2.0 ghz figure 18 ? rf out2 insertion loss variation across phase state (*) note: * across recommended rf out2 phase states for minimum insertion loss variation. -8 -7.8 -7.6 -7.4 -7.2 -7 -6.8 -6.6 -6.4 -6.2 -6 0 102030405060708090100 insertion loss (db) phase state (deg) 2.0 ghz
PE46120 monolithic phase & amplitude controller doc-54655-6 C (5/2015) page 19 www.psemi.com figure 19 ? rf out2 phase variation across rf out2 attenuation state -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 phase (deg) attenuation state (db) 1.8 ghz 2.0 ghz 2.2 ghz
PE46120 monolithic phase & amplitude controller page 20 doc-54655-6 C (5/2015) www.psemi.com figure 20 ? rf out2 insertion loss across rf out2 attenuation state vs v dd , frequency = 2 ghz -16 -14 -12 -10 -8 -6 -4 -2 0 00.511.522.533.544.555.566.577.5 insertion loss (db) attenuation state (db) 2.3v 3.3v 5.5v figure 21 ? rf out2 insertion loss across rf out2 attenuation state vs temperature, frequency = 2 ghz -16 -14 -12 -10 -8 -6 -4 -2 0 00.511.522.533.544.555.566.577.5 insertion loss (db) attenuation state (db) -40c +25c +85c +105c
PE46120 monolithic phase & amplitude controller doc-54655-6 C (5/2015) page 21 www.psemi.com figure 22 ? rf out2 relative phase across rf out2 phase state vs v dd , frequency = 2 ghz -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 102030405060708090 relative phase (deg) phase state (deg) 2.3v 3.3v 5.5v figure 23 ? rf out2 relative phase across rf out2 phase state vs temperature, frequency = 2 ghz -90 -80 -70 -60 -50 -40 -30 -20 -10 0 0 102030405060708090 relative phase (deg) phase state (deg) -40c +25c +85c +105c
PE46120 monolithic phase & amplitude controller page 22 doc-54655-6 C (5/2015) www.psemi.com pin information this section provides pinout information for the PE46120. figure 24 shows the pin map of this device for the available package. table 11 provides a description for each pin. figure 24 ? pin configuration (top view) exposed ground pad rf out2 nc nc nc nc nc nc nc v dd le sdi v dd le sdi nc ds sp enb gnd rf out1 rf out1 nc rf out2 clk nc rf in rf in nc sdo clk sdo 1 3 4 5 6 7 8 2 9 11 12 13 14 15 16 10 32 30 29 28 27 26 25 31 24 22 21 20 19 18 17 23 nc nc pin 1 dot marking table 11 ? pin descriptions for PE46120 pin no. pin name description 1, 8 clk (1) clock input 2, 7 sdo (2) serial data output 3, 6, 12?16, 22, 25?29 nc no connect 4, 5 rf in (3) rf input 9, 32 sdi (1) serial data input 10, 31 le (1) latch enable 11, 30 v dd (1) supply voltage 17, 18 rf out1 (3) rf output 1 19 gnd (4) ground 20 sp enb (5)(6) serial port enable 21 ds (6) default state at power up select 23, 24 rf out2 (3) rf output 2 pad gnd exposed pad: ground for proper oper- ation notes: 1) pins are internally connected, signal only needs to be applied to one of the pins. the alternate unused pin needs to be left floating. 2) sdos are independently buffered outputs of the same signal. 3) rf pins 4, 5, 17 and 18 must be at 0 vdc. the rf pins do not require dc blocking capacitors for proper operation if the 0 vdc requirement is met. 4) pin 19 must be grounded for proper function. 5) must be active low for normal spi operation. logic high programs 0 db attenuation setting and 0 phase setting. setting back to logic low returns to the previously programmed state. 6) pin has an internal 100 k ? pull-up resistor.
PE46120 monolithic phase & amplitude controller doc-54655-6 C (5/2015) page 23 www.psemi.com packaging information this section provides packaging data including the moisture sensitivity level, package drawing, package marking and tape-and-reel information. moisture sensitivity level the moisture sensitivity level rating for the PE46120 in the 32-lead 6 6 mm qfn package is msl1. package drawing top-marking specification figure 25 ? package mechanical drawing for 32-lead 6 6 0.85 mm qfn figure 26 ? package marking specifications for PE46120 top view bottom view side view recommended land pattern a 0.10 c (2x) c 0.10 c 0.05 c seating plane b 0.10 c (2x) 0.10 c a b 0.05 c all features pin #1 corner 6.000.05 6.000.05 4.300.05 4.300.05 0.50 0.200.05 (x32) 0.400.05 (x32) 3.50 ref. 0.850.05 0.05 max 0.203 ref. (x28) 4.35 4.35 0.85 (x32) 0.25 (x32) 0.50 (x28) 6.75 6.75 = yy = ww = zzzzzzzz = pin 1 indicator last two digits of assembly year assembly work week assembly lot code (maximum eight characters) 46120 yyww zzzzzzzz
PE46120 monolithic phase & amplitude controller page 24 doc-54655-6 C (5/2015) www.psemi.com tape and reel specification figure 27 ? tape and reel specifications for 32-lead 6 6 0.85 mm qfn device orientation in tape pin 1 t k0 a0 b0 p0 p1 d1 a section a-a a direction of feed d0 e w0 p2 see note 3 see note 1 f see note 3 a0 b0 k0 d0 d1 e f p0 p1 p2 t w0 6.30 0.10 6.30 0.10 1.10 0.10 1.50 + 0.1/ -0.0 1.5 min 1.75 0.10 7.50 0.10 4.00 12.00 0.10 2.00 0.10 0.30 0.05 16.00 0.30 notes: 1. 10 sprocket hole pitch cumulative tolerance 0.2 2. camber in compliance with eia 481 3. pocket position relative to sprocket hole measured as true position of pocket, not pocket hole dimensions are in millimeters unless otherwise specified
PE46120 product specification www.psemi.com doc-54655-6 C (5/2015) document categories advance information the product is in a formative or design stage. the datasheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the datasheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the datasheet contains final data. in the event peregrine decides to change the specifications, peregri ne will notify customers of the intended changes by issuing a cnf (customer notification form). not recommended for new designs (nrnd) this product is in production but is not recommended for new designs. end of life (eol) this product is currently going th rough the eol process. it has a specific last-time buy date. obsolete this product is discontinued. orde rs are no longer accepted for this product. sales contact for additional information, contact sales at sales@psemi.com. disclaimers the information in this datasheet is believed to be reliable. however, peregrine assumes no liability for the use of this infor mation. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this datasheet are implied or grante d to any third party. peregrine?s products are not designed or intended for use in devi ces or systems intended for surgical implant, or in other appl ications intended to support or sustain life, or in any applicati on in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, incl uding consequential or incidental damages, aris ing out of the use of its products in such applications. patent statement peregrine products are protected under one or more of the following u.s. patents: patents.psemi.com copyright and trademark ?2014-2015, peregrine semiconductor corporation. all rights rese rved. the peregrine name, logo, utsi and ultracmos are register ed trade- marks and harp, multiswitch and dune are tr ademarks of peregrine semiconductor corp. ordering information table 12 lists the available ordering codes for the PE46120 as well as available shipping methods. product specification table 12 ? order codes for PE46120 order codes description packaging shipping method PE46120a-x PE46120 monolithic phase and amplitude controller green 32-lead 6 6 mm qfn 500 units / t&r ek46120-02 PE46120 evaluation kit evaluation kit 1 / box

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